
/*!
    \file  sfc_gd32wq.h
    \brief definitions for sfc based qspi flash chip gd32wq

    \version 2024-04-12, V1.0.0, firmware for LINK32FA016BX
*/



#ifndef LINK32FA016BX_SFC_GD32WQ_H
#define LINK32FA016BX_SFC_GD32WQ_H

#include "link32fa016bx_sfc.h"

LINK32FA016BX_BEGIN_DECLS

#define FLASH_WRITE_ENABLE(op) \
	(op).cmd = 0x06; \
	(op).cmd_phase = 0x1;

#define FLASH_WRITE_DISABLE(op) \
	(op).cmd = 0x04; \
	(op).cmd_phase = 0x1;

#define FLASH_RD_STATUS_REG1(op) \
	(op).cmd = 0x05; \
	(op).cmd_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_dir = SFC_DIR_RX_ONLY;

#define FLASH_RD_STATUS_REG2(op) \
	(op).cmd = 0x35; \
	(op).cmd_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_dir = SFC_DIR_RX_ONLY;

#define FLASH_RD_STATUS_REG3(op) \
	(op).cmd = 0x15; \
	(op).cmd_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_dir = SFC_DIR_RX_ONLY;


#define FLASH_WR_STATUS_REG1(op) \
	(op).cmd = 0x01; \
	(op).cmd_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_dir = SFC_DIR_TX_ONLY;

#define FLASH_WR_STATUS_REG2(op) \
	(op).cmd = 0x31; \
	(op).cmd_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_dir = SFC_DIR_TX_ONLY;

#define FLASH_WR_STATUS_REG3(op) \
	(op).cmd = 0x11; \
	(op).cmd_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_dir = SFC_DIR_TX_ONLY;

#define FLASH_VOL_SR_WR_ENABLE(op) \
	(op).cmd = 0x50; \
	(op).cmd_phase = 0x1;

#define FLASH_READ_DATA(op) \
	(op).cmd = 0x03; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).addr_bytes = 3; \
	(op).data_dir = SFC_DIR_RX_ONLY;

#define FLASH_FAST_READ(op) \
	(op).cmd = 0x0B; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).dummy_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).addr_bytes = 3; \
	(op).dummy_bytes = 1; \
	(op).data_dir = SFC_DIR_RX_ONLY;

#define FLASH_DUAL_OUTPUT_FAST_READ(op) \
	(op).cmd = 0x3B; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).dummy_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_speed = SFC_SPEED_DPI; \
	(op).addr_bytes = 3; \
	(op).dummy_bytes = 1; \
	(op).data_dir = SFC_DIR_RX_ONLY;

#define FLASH_QUAD_OUTPUT_FAST_READ(op) \
	(op).cmd = 0x6B; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).dummy_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).data_speed = SFC_SPEED_QPI; \
	(op).addr_bytes = 3; \
	(op).dummy_bytes = 1; \
	(op).data_dir = SFC_DIR_RX_ONLY;

#define FLASH_PAGE_PROGRAM(op) \
	(op).cmd = 0x02; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).data_phase = 0x1; \
	(op).addr_bytes = 3; \
	(op).dummy_bytes = 1; \
	(op).data_dir = SFC_DIR_TX_ONLY;

#define FLASH_SECTOR_ERASE(op) \
	(op).cmd = 0x20; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).addr_bytes = 3;

#define FLASH_BLOCK_ERASE_32K(op) \
	(op).cmd = 0x52; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).addr_bytes = 3;

#define FLASH_BLOCK_ERASE_64K(op) \
	(op).cmd = 0xD8; \
	(op).cmd_phase = 0x1; \
	(op).addr_phase = 0x1; \
	(op).addr_bytes = 3;

#define FLASH_CHIP_ERASE(op) \
	(op).cmd = 0xC7; \
	(op).cmd_phase = 0x1;

uint8_t flash_read_status_reg1();
uint8_t flash_read_status_reg2();
uint8_t flash_read_status_reg3();
void flash_write_enable();
void flash_write_disable();
void flash_sector_erase(uint32_t addr);
void flash_block_erase_32k(uint32_t addr);
void flash_block_erase_64k(uint32_t addr);
void flash_chip_erase();
ErrStatus flash_program(uint32_t xts_bypass, uint32_t addr, uint32_t data_bits, uint8_t *data);
ErrStatus flash_read(uint32_t xts_bypass, uint32_t addr, uint32_t data_bits, uint8_t *data);
ErrStatus flash_fast_read(uint32_t xts_bypass, uint32_t addr, uint32_t data_bits, uint8_t *data);
ErrStatus flash_dual_output_fast_read(uint32_t xts_bypass, uint32_t addr, uint32_t data_bits, uint8_t *data);
ErrStatus flash_quad_output_fast_read(uint32_t xts_bypass, uint32_t addr, uint32_t data_bits, uint8_t *data);

LINK32FA016BX_END_DECLS


#endif //LINK32FA016BX_SFC_GD32WQ_H
